This invention relates to constant voltage generating circuits, and more particularly to a constant voltage generating circuit in the form of a semiconductor integrated circuit.
In the following description, insulated gate field-effect transistors will be referred to as "MOS transistors", when applicable.
One example of a conventional constant voltage generating circuit is as shown in FIG. 5. In this circuit, a predetermined voltage is applied to a power source terminal 1, and a series circuit of a resistor 3 having a resistance R.sub.3 and a resistor 4 having a resistance R.sub.4 is connected between the terminal 1 and ground. The connecting point 2 of the resistors 3 and 4 is an output terminal from which the output voltage of the constant voltage generating circuit is applied. A decoupling capacitor 5 for stabilizing the output voltage at the output terminal 2 is connected between the connecting point 2 and ground.
The operation of the conventional constant voltage generating circuit thus organized will now be described.
In the circuit of FIG. 5, the output voltage at the output terminal 2 is determined from the supply voltage at the power source terminal 1 and the resistance of the resistors 3 and 4. That is, the output voltage V.sub.2 at the output terminal 2 is: ##EQU1## where V is the supply voltage at the power source terminal 1.
As is apparent from equation (1), the output voltage V.sub.2 changes in proportion to the supply voltage V. Therefore, the constant voltage generating circuit in FIG. 5 is employed as a voltage source where it is acceptable for the output voltage to follow the supply voltage, such as a reference voltage source in a sense amplifier circuit for a dynamic random access memory.
FIG. 6 shows another example of a conventional constant voltage generating circuit. In the circuit of FIG. 6, a predetermined voltage is applied to a power source terminal 11, and a series circuit of a resistor 13 and a plurality of N-type MOS transistors 16a through 16n is connected between the terminal 11 and ground. In each of the MOS transistors, the drain electrode is connected to the gate electrode. Each of the MOS transistors has a threshold voltage V.sub.THN. The connecting point 12 of the resistor 13 and the N-type MOS transistor 16a, i.e., an output terminal, is grounded through a decoupling capacitor 15 adapted to stabilize the output voltage at the output terminal 12.
The operation of the circuit shown in FIG. 6 will be now described. In the case where the resistance of the resistor 13 is higher than the resistance of the N-type MOS transistors 16a through 16n which are turned on, then the output voltage V.sub.12 at the output terminal 12 is: EQU V.sub.12 .apprxeq.n.multidot.V.sub.THN ( 12)
Accordingly, the output voltage V.sub.12 is maintained constant irrespective of the variation of the supply voltage at the power source terminal 11. Therefore, the constant voltage generating circuit in FIG. 6 is employed as a voltage source in which the output voltage is independent of the supply voltage, such as a reference voltage source for a MOS side differential amplifier circuit in the transition from TTL level to MOS level.
In the circuit of FIG. 5, a DC current flows through the resistors 3 and 4. In the circuit of FIG. 6, a DC current flows through the resistor 13 and the N-type MOS transistors 16a through 16n. Therefore, it is necessary to increase the resistance of the resistors 3, 4 and 13 as much as possible (several megohms to several tens of megohms) to decrease the DC currents as much as possible, to thereby minimize the power consumption of the circuits. However, if the resistances are increased, then the output voltage are liable to be affected by noise which is produced in the operation of the integrated circuit. Therefore, the output voltage must be stabilized by connecting a decoupling capacitor (generally 10 pF to 100 pF) such as the capacitor 5 in FIG. 5 or the capacitor 15 in FIG. 15. Such a decoupling capacitor occupies a relatively large part of the area of the semiconductor chip. This is one of the difficulties accompanying the conventional constant voltage generating circuit.
In a dynamic random access memory to which the above-described constant voltage generating circuits can be applied supply voltage variation is commonly tested by repeatedly increasing and decreasing the supply voltage between 4.5 V and 5.5 V. In this connection, the conventional constant voltage generating circuits suffer from the difficulty that, because of the large resistance and the large stabilizing capacitance, the output voltage of the constant generating circuit cannot quickly follow the variation of the supply voltage; that is, it takes time for the output voltage to reach the predetermined value, as a result of which the time required for a supply voltage variation test is unavoidably long.